Low Power Cmos Full Adder Design with 12 Transistors

In present work two new designs for single bit full adders have been presented using three transistors XOR gates. Adder having twelve transistors shows power consumption of 1274μW with maximum output delay of 0.2049ns. Power consumption and maximum output delay shows variation [1274 141.77] μW & [0.2049 – 0.4167] ns with varying supply voltage from [3.3 1.8] V. Further, reverse body bias technique for power reduction has been applied to adder. Adder with reverse body bias shows power consumption variations of [1270 1067.60] μW with varying NMOS reverse bias from [0.0 to 2.0] V. Delay of adder shows variations [0.2049 0.2316] ns with reverse bias variation [0.0 to 2.0] V. Simulations have been carried out at different supply voltage with increasing reverse biased applied to NMOS transistor and results shows improvements in power consumption of adder. A comparison with earlier reported circuits have been presented and proposed circuit’s shows less power dissipation.